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data sheet 700mhz, femtoclock ? vcxo based sonet/sdh jitter attenuators 843002I-41 843002I-41 rev b 9/4/14 1 ?2014 integrated device technology, inc. general description the ics843002I-41 is a pll based synchronous clock generator that is optimized for sonet/s dh line card applications where jitter attenuation and frequency translation is needed. the device contains two internal pll stages that are cascaded in series. the first pll stage uses a vcxo which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd pll stage (typically 19.44mhz). the second pll stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise femtoclock? vco. pll multiplication ratios are selected from internal lookup tables using device input selection pins. the device performance and the pll multiplication ratios are optimized to support non-fec (non-forward error correction) sonet/sdh applications with rates up to oc-48 (sonet) or stm-16 (sdh). the vcxo requir es the use of an external, inexpensive pullable crystal. vcxo pll uses external passive loop filter components which are used to optimize the pll loop bandwidth and damping characteristics for the given line card application. the ics843002I-41 includes two clock input ports. each one can accept either a single-ended or differential input. each input port also includes an activity detector circuit, which reports input clock activity through the lor0 and lor1 logic output pins. the two input ports feed an input select ion mux. ?hitless switching? is accomplished through proper filter tuning. jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks. typical ics843002I-41 configur ation in sonet/sdh systems: ? vcxo 19.44mhz crystal ? input reference clock frequency selections: 19.44mhz, 38.88mhz, 77.76mhz , 155.52mhz, 311.04mhz, 622.08mhz ? output clock frequency selections: 19.44mhz, 77.76mhz, 155.52mhz, 311.04mhz, 622.08mhz, hi-z features two differential lvpecl outputs selectable clkx, nclkx differential input pairs clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl or single-ended lvcmos or lvttl levels maximum output frequency: 700mhz femtoclock vco frequency range: 560mhz - 700mhz rms phase jitter @ 155.52mhz , using a 19.44mhz crystal (12khz to 20mhz): 0.81ps (typical) full 3.3v or mixed 3.3v core/2.5v output operating supply -40c to 85c ambient operating temperature available in lead-free (rohs 6) package pin assignment ics843002I-41 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 12 3 4 56 7 8 2423 22 21 2019 18 17 lf1 lf0 iset v cc clk0 nclk0 clk_sel qa_sel2 lor0 lor1 nc v cco_lvcmos v cco_lvpecl nqb qb v ee qa_sel1 qa_sel0 qb_sel2 qb_sel1 qb_sel0 v cca qa nqa xtal_out r_sel2 r_sel1r_sel0 v ee clk1nclk1 xtal_in
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 2 rev b 9/4/14 843002I-41 data sheet block diagram r divider = 1, 2, 4, 8, 16 or 32 clk1 nclk1 activity detector clk0 nclk0 activity detector lor1 lor0 r_sel2:0 3 iset clk_sel femtoclock pll x32 622.08 mhz v cco_pecl qa nqa cx divider = 1,2,4,8,16,32, hiz or disable qb nqb qb_sel2:0 qa_sel2:0 3 3 vcxo charge pump and loop filter external loop components 19.44 mhz pullable xtal 19.44 mhz xtal_in xtal_out lf1 lf0 divide by 32 divide by 32 vcxo jitter attenuation pll phase detector ics843002I-41 110 110 111 111 v cco_lvcmos 1 0 cx divider = 1,2,4,8,16,32, hiz or disable note: 19.44mhz vcxo crystal shown is typical for sonet/sdh device applications.
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 3 rev b 9/4/14 843002I-41 data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 2 lf1, lf0 analog input/output loop filter connection node pins. 3 iset analog input/output charge pump current setting pin. 4v cc power core power supply pin. 5 clk0 input pulldown non-inverting differential clock input. 6n c l k 0i n p u t pullup pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 7 clk_sel input pulldown input clock select. lvcmos/lvttl interface levels. see table 3a. 8 qa_sel2 input pulldown output divider control fo r qa/nqa lvpecl outputs. lvcmos/lvttl interface levels.see table 3c. 9, 10 qa_sel1, qa_sel0 input pullup output divider control fo r qa/nqa lvpecl outputs. lvcmos/lvttl interface levels.see table 3c. 11 qb_sel2 input pulldown output divider control fo r qb/nqb lvpecl outputs. lvcmos/lvttl interface levels.see table 3c. 12, 13 qb_sel1, qb_sel0 input pullup output divider control fo r qb/nqb lvpecl outputs. lvcmos/lvttl interface levels.see table 3c. 14 v cca power analog supply pin. 15, 16 qa, nqa output differential clock ou tput pair. lvpecl interface levels. 17, 27 v ee power negative supply pins. 18, 19 qb, nqb output differential clock ou tput pair. lvpecl interface levels. 20 v cco_lvpecl power output supply pi n for lvpecl outputs. 21 v cco_lvcmos power output supply pin for lvcmos/lvttl outputs. 22 nc unused no connect. 23 lor1 output alarm output, loss of refe rence for cl k1/nclk1. lvcmos/lvttl interface levels. 24 lor0 output alarm output, loss of refe rence for cl k0/nclk0. lvcmos/lvttl interface levels. 25 nclk1 input pullup pulldown inverting differential clock input. v cc /2 bias voltage when left floating. 26 clk1 input pulldown non-inverting differential clock input. 28, 29, 30 r_sel0, r_sel1, r_sel2 input pulldown input divider selection. lvcmos/lvttl interface levels. see table 3b. 31, 32 xtal_out, xtal_in input crystal oscillator interface. the xtal_in is the input. xtal_out is the output.
rev b 9/4/14 4 700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet table 2. pin characteristics function tables table 3a. input reference selection function table table 3b. input reference divider selection function table table 3b. output divider selection function table symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k ? input function clk_sel inpu t selected 0 clk0/nclk0 1 clk1/nclk1 inputs function r_sel2 r_sel1 r_sel0 r di vider value or state 000 1 001 2 010 4 011 8 100 1 6 101 3 2 1 1 0 bypass vcxo pll 1 1 1 bypass vcxo and femtoclock plls inputs function qx_sel2 qx_sel1 qx_sel0 output divider value or state 0 0 0 output qx/nqx (hi-z) 001 3 2 010 8 011 4 100 1 6 101 2 110 1 1 1 1 output qx at lvpecl v ol, output nqx at lvpecl v oh
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 5 rev b 9/4/14 843002I-41 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v5%, v cco_lvcmos, v cco_lvpecl = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) outputs, i o (lvpecl) continuos current surge current -0.5v to v cco_lvcmos + 0.5v 50ma 100ma package thermal impedance, ? ja 37 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.15 3.3 v cc v v cco_lvcmos, v cco_lvpecl output supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v i ee power supply current 210 ma i cca analog supply current 15 ma
rev b 9/4/14 6 700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v5%, v cco_lvcmos = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c table 4c. differential dc characteristics, v cc = 3.3v5%, v cco_lvpecl = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c note 1: v il cannot be less than -0.3v note 2: common mode input voltage is defined as v ih . table 4d. lvpecl dc characteristics, v cc = v cco_lvpecl = 3.3v5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco_lvpecl ? 2v. see parameter measurement information section, output load test circuit diagram . symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current qa_sel[0:1], qb_sel[0:1] v cc = v in = 3.465v 5 a clk_sel, qa_sel2, qb_sel2, r_sel[0:2] v cc = v in = 3.465v 150 a i il input low current qa_sel[0:1], qb_sel[0:1] v cc = 3.465v, v in = 0v -150 a clk_sel, qa_sel2, qb_sel2, r_sel[0:2] v cc = 3.465v, v in = 0v -5 a v oh output high voltage lor0, lor1 v cco_lvcmos = 3.465v, i oh = 1ma 2.6 v v cco_lvcmos = 2.625v, i oh = 1ma 1.8 v v ol output low voltage lor0, lor1 v cco_lvcmos = 3.465v or 2.625v, i ol = -1ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0/nclk0,clk1/nclk1 v cc = v in = 3.465v 150 a i il input low current clk0, clk1 v cc = 3.465v, v in = 0v -5 a nclk0, nclk1 v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 7 rev b 9/4/14 843002I-41 data sheet table 4e. lvpecl dc characteristics, v cc = 3.3v5%, v cco_lvpecl = 2.5v5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco_lvpecl ? 2v. see parameter measurement information section, output load test circuit diagram . ac electrical characteristics table 5. ac characteristics, v cc = 3.3v5%, v cco_lvcmos = v cco_lvpecl = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c see parameter measurement information section. note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions. measured at the output differential cross points. note 2: this parameter is defined in accordance with jedec standard 65. note 3: please refer to the phase noise plots. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.4 1.0 v symbol parameter test conditions minimum typical maximum units f out output frequency 19.44 700 mhz t sk(o) output skew; note 1, 2 150 ps t jit(?) rms phase jitter (random); note 3 155.52mhz, integration range: 12khz ? 20mhz 0.81 ps t r / t f output rise/fall time 20% to 80% 100 800 ps odc output duty cycle 45 55 %
rev b 9/4/14 8 700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet typical phase noise at 155.52mhz filter phase noise result by adding a filter to raw data raw phase noise data 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.81ps (typical) offset frequency (hz) noise power dbc hz ? ? ?
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 9 rev b 9/4/14 843002I-41 data sheet parameter measureme nt information 3.3v core/3.3v lvpecl output load ac test circuit differential input level rms phase jitter 3.3v core/2.5v lvpecl outp ut load ac test circuit output skew output rise/fall time 2v -1.3v 0.165 2v v cc, v cca v cco_lvpecl, v cco_lvcmos nclk0, nclk1 clk0, clk1 v cmr cross points v pp v cc v ee phase noise mask offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power scope qx nqx v ee v cc, 2v -0.5v 0.125 v cca v cco_lvpecl 2.8v0.04 2.8v0.04 v cco_lvcmos nqx qx nqy qy nqa, nqb qa, qb
rev b 9/4/14 10 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet output duty cycle/pulse width/period application information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clkx and nclkx can be left floatin g. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. nqa, nqb qa, qb
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 11 rev b 9/4/14 843002I-41 data sheet power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics843002I-41 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca, v cco_lvpecl and v cco_lvcmos should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v cca pin. figure 1. power supply filtering wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ended signal driving differential input v_ref single ended clock input v cc clkxnclkx r11k c1 0.1u r2 1k
rev b 9/4/14 12 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 3b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 3f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r150 r250 1.8v zo = 50 zo = 50 clknclk 3.3v lvhstlidt lvhstl driver differentialinput h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clknclk differentialinput sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1120 r2120 r3120 r4120
rev b 9/4/14 13 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
rev b 9/4/14 14 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v +_
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 15 rev b 9/4/14 843002I-41 data sheet termination for 2.5v lvpecl outputs figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 6b can be eliminated and the termination is shown in figure 6c. figure 6a. 2.5v lvpecl driver termination example figure 6c. 2.5v lvpecl driver termination example figure 6b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + ?
rev b 9/4/14 16 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet schematic example figure 7 shows a schematic example of the ics843002I-41 application schematic. in this exam ple, the device is operated at vcc = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver. the 2-pole filter example is used in this schematic. please refer to the ics843002I-41 datashe et for additional loop filter recommendations. figure 7. ics843002I-41 schematic example loss of reference indicator (l or0 and lor1) output pins the lor0 and lor1 pins are controlled by the internal clock activity monitor circuits. the cloc k activity monitor circuits are clocked by the vcxo pll phase detector feedback clock. the lor output is asserted high if there are three consecutive feedback clock edges without any reference clock edges (in both cases, either a negative or positive transition is counted as an ?edge?). the lor output will otherwise be low. in a phase detector observation interval, the activity monitor does not flag excessive reference transitions as an error. the monitor only distinguishes between transitions occurring and no transitions occurring.
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 17 rev b 9/4/14 843002I-41 data sheet vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a crystal, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines it resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal (c l ) is lower than the total external capacitance, the vcxo will oscillate at a lower frequency than the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the vcxo-pll loop bandwidth selection table shows r s , c s and c p values for recommended high, mid and low loop bandwidth configurations. the device has been characterized using these parameters. for other configurations, refer to the loop filter component selection for vcxo based plls application note. the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. vcxo characteristics table vcxo-pll loop bandwidth selection table crystal characteristics lf0lf1 iset xtal_in xtal_out r s c s c p r set c tune c tune 19.44mhz symbol parameter typical units k vcxo vcxo gain 5800 hz/v c v_low low varactor capacitance 12.6 pf c v_high high varactor capacitance 24.5 pf bandwidth crystal frequency (mhz) r s (k ? )c s (f) c p (f) r set (k ? ) 10hz (low) 19.44 5 1.0 0.10 9.5 70hz (mid) 19.44 10 1.0 0.01 4.75 100hz (high) 19.44 15 1.0 0.01 4.75 symbol parameter test conditions minimum typical maximum units mode of oscillation fundamental f n frequency 19.44 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range -40 +85 0 c c l load capacitance 12 pf c o shunt capacitance 4 pf c o / c 1 pullability ratio 220 240 esr equivalent series resistance 50 ? drive level 1m w aging @ 25 0 c 3 per year ppm
rev b 9/4/14 18 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet power considerations this section provides information on power dissipati on and junction temperature for the ics843002I-41. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843002I-41 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 210ma = 727.65mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power_ max (3.3v, with all outputs switching) = 727.65mw + 60mw = 787.65mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.788w * 37c/w = 114.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ? ja for 48 lead tqfp, forced convection ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 19 rev b 9/4/14 843002I-41 data sheet 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 8. figure 8. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
rev b 9/4/14 20 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet reliability information table 7. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ics843002I-41 is: 5536 ? ja vs. air flow meters per second 012 . 5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 21 rev b 9/4/14 843002I-41 data sheet package outline and package dimensions package outline - k suffix for 32-lead vfqfn note: the following package mechanical drawing is a generic drawin g that applies to any pin count vfqfn package. this drawing i s not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8 below. table 8. package dimensions reference document: jede c publication 95, mo-220 jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00 . 0 5 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 12 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion or sa wn s ing u l a tion
rev b 9/4/14 22 700mhz, femtoclo ck? vcxo based sonet/sdh jitter attenuator 843002I-41 data sheet ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843002aki-41lf ics002ai41l ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 843002aki-41lft ics002ai41l ?lead-free? 32 lead vfqfn 2500 tape & reel -40 ? c to 85 ? c
700mhz, femtoclock? vcxo based sonet/sdh jitter attenuator 23 rev b 9/4/14 843002I-41 data sheet revision history sheet rev table page description of change date a t4b 6 lvcmos dc characteristics table - added conditions to v oh and v ol . 1/22/09 b 5 7 ac characteristics table - changed output skew from 50 to 150 4/7/09 b t9 1 22 general description - removed loop bandwidth bullet removed reference to leaded devices ordering information - removed leaded devices updated datasheet format 4/9/14
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